High-speed printed circuit board stack design

Introduction: Designing high-speed printed circuit boards, the most important thing is to grasp the design of high-speed circuit board in the three elements: First, the high-speed circuit board stack design; Second, the board signal line impedance control; Third, multi-load interconnection signal line Topological structure. How do you consider the three most basic elements in the design of high-speed circuit board, it is half successful. Of course, more in-depth aspects are also of concern, such as: timing analysis of high-speed interconnection interfaces; analysis of the skin effect of Ghz signals; thermal analysis; analysis of electromagnetic radiation, etc. Factors that need to be considered are many. This article will start from the simplest example of a four-layer board to discuss the cascade design of high-speed circuit boards.

First, the content and principles of stack design need to be considered

The most basic things to consider in the design of a stack design are:
First, the distribution of high-speed signal layers;
Second, the distribution of strata;
Third, the distribution of the power layer.

If the number of layers on the circuit board is greater, the types of permutations and combinations of high-speed signal layers, strata, and power layers are also greater. Even a simple four-layer board can have several combinations (discussed later). What kind of combination is best for your product design? This requires a series of evaluations. But there are only two general principles:

The first: High-speed signal lines such as in the outer layer (TOP/BOTTOM) must make these signal lines form microstrip lines. If high-speed signal lines are in the inner layer, these signal lines must be made up of microstrip lines or strip lines.
Article 2: Good coupling between the power layer and the ground layer is required to reduce the impedance between the power layer and the ground layer as much as possible while increasing the resonant frequency of the power layer and the stratum structure.

Two or four layer stack design analysis

In the multilayer board, the simplest one is the four-layer board. Now we will use the four-layer board as an example to analyze the stack design, to help us with 6, 8, 10, and 12. . . Multilayer laminate design.

Four-layer board is relatively simple, there are only three commonly used stacking methods, as follows:

TOP ――――――――――――――― Signal
Inter1 ――――――――――――――― GND
Inter2 ――――――――――――――― POWER
BOTTOM —————————————— Signal2

TOP ――――――――――――――――― Signal1
Inter1 ――――――――――――――― POWER
Inter2 ――――――――――――――― GND
BOTTOM —————————————— Signal2

TOP ――――――――――――――― GND
Inter1 ――――――――――――― Signal1
Inter2 ――――――――――――――― GND
BOTTOM —————————————— Signal2

Doing four-tier board will know. We should use the most of option one. Why did you choose it? Is everything else bad? In actual fact, sometimes I still need to use Option 2 to compare my own products. Of course, Option 3 is relatively poor. How to choose? Don't forget the two basic principles we mentioned above.

The first: As long as the GND layer, POWER layer integrity is not divided into three stacking schemes can basically meet. It seems that the second article: Good coupling between the power layer and the stratum is the key to selecting a four-layer circuit board. From the stack up, the coupling between the power plane and the formation in scheme 3 is the worst and can be eliminated immediately.

But how should Option 1 and Option 2 be chosen? Let us specifically substituting the various parameters of the circuit board, as shown below:

TOP ――――――――――――――――― Signal 1.9mi
2116 4.5mil
Inter1 ――――――――――――― GND 1.2mil
Core 44.5 mi
Inter2 ――――――――――――― POWER 1.2mil
2116 4.5mil
BOTTOM ――――――――――――――――― Signal2 1.9mil

This is a four-layer board with 1.5mm thickness and 50Ω line impedance control. From the above data, we can know that whether it is scheme 1 or scheme 2, the direct distance between the power source and the ground is very large 44.5mil. To ensure a good coupling between the power supply and the ground, the best way for solution 1 is to use fewer BOTTOM signal lines and to spread large areas of ground copper to the power layer. The best way for scheme 2 is that there is less signal at the TOP layer, and a large area of ​​ground copper can be well coupled with the power layer. From the above analysis, we can easily draw the following conclusion: If most of our high-speed signal traces can be processed in TOP, we should use Option 1. Similarly, if most of our high-speed signal traces can be processed at BOTTOM, we should use Option 2.

Of course, 6, 8, 10, and 12. . . The layer stack design needs to consider more



Author: Ye En Qi Source: Shanghai Tai Qi Technology